Evaluating the Potential of Programmable Multiprocessor Cache Controllers

The next generation of scalable parallel systems e g machines by KSR Convex and others will have shared memory supported in hardware unlike most current generation machines e g o erings by Intel nCube and Thinking Machines However current shared memory architectures are constrained by the fact that their cache controllers are hardwired and in exible which limits the range of programs that can achieve scalable performance This observation has led a number of researchers to propose building programmable multiprocessor cache controllers that can implement a variety of caching protocols support multiple communication paradigms or accept guidance from software To evaluate the potential performance bene ts of these designs we have simulated ve SPLASH benchmark programs on a virtual multiprocessor that supports ve directory based caching protocols When we compared the o line optimal performance of this design wherein each cache line was maintained using the protocol that required the least communication with the performance achieved when using a single protocol for all lines we found that use of the optimal protocol reduced consistency tra c by with a mean improvement of Cache miss rates also dropped by up to Thus the combination of programmable or tunable hardware and software able to exploit this added exibility e g via user pragmas or compiler analysis could dramatically improve the performance of future shared memory multiprocessors Evaluating the Potential of Programmable Multiprocessor Cache Controllers John B Carter Mike Hibler Ravindra R Kuramkote Department of Computer Science University of Utah